Semiconductor memory devices can be categorized as either volatile memory devices or nonvolatile memory devices according to whether or not data is retained when power supplies are interrupted. The volatile memory devices may be classified into a dynamic random access memory (DRAM) and a static random access memory (SRAM). The nonvolatile memory devices include flash memory devices. These memory devices represent a logic value, such as “0” or “1,” based on stored charge. Because a periodic refresh operation is typically needed for such devices, a DRAM may require a high charge storage capacitance. Consequently, there have been attempts to increase a surface area of a capacitor electrode to increase storage capacitance. However, an increase in the surface area of the capacitor electrode can interfere with an increase in integration of the DRAM.
A typical flash memory device has gate patterns including a gate insulating layer, a floating gate, a dielectric layer, and a control gate, which are sequentially stacked on a semiconductor substrate. To write and erase data, a method of tunneling charges through the gate insulating layer is used at a voltage that is higher than the normal power supply voltage. Accordingly, flash memory devices typically require a booster circuit in order to produce the voltage for erase and write operations.
As memory devices become highly integrated, many efforts have been underway to develop a new memory device having nonvolatile and random access characteristics, and a simple structure. Phase-changeable memory devices are one type of such memory devices. A typical phase-changeable memory device has a cell made of a phase-changeable material. Depending on a provided current density (i.e., Joule heating), the phase-changeable material can be electrically switched between amorphous and crystalline states and/or between variously resistive crystalline states.
FIG. 1 is a graph showing a method of programming and erasing a phase-changeable memory cell. Here, a horizontal axis represents time (T) an axis represents temperature (TMP: ° C.) applied to the phase-changeable material cell. The phase-changeable material is heated at a temperature that is higher than a melting temperature Tm during a relatively short first time T1. Next, the phase-changeable material is rapidly quenched. In this case, the phase-changeable material may be changed into the amorphous state (curve 1). During a second time T2 that is longer than the first time T1, the phase-changeable material is heated at a temperature that is lower than the melting temperature Tm and is higher than a crystallization temperature Tc. Next, the phase-changeable material is quenched. In this case, the phase-changeable material is changed into the crystalline state (curve 2). The resistivity of the phase-changeable material with the amorphous state is higher than that of the phase-changeable material with the crystalline state. Accordingly, currents flowing through the phase-changeable material may be detected in a read mode, and it is possible to discriminate whether information stored in the phase-changeable memory cell has a logic value of “1” or “0”. Generally, a chalcogenide material is used as the phase-changeable material, in particular, a compound (hereinafter a “GST layer”) including germanium (Ge), stibium (Sb), and tellurium (Te).
As described above, heat is typically needed in order to switch the state of the phase-changeable material. In the typical phase-changeable memory device, if currents of a high density flow through an area contacting the phase-changeable material, a crystallization state of the phase-changeable material at a contact area is varied. The smaller the contact area is, the lower the current density for changing the state of the phase-changeable material.
FIG. 2 is a cross-sectional view for explaining a typical phase-changeable memory device structure, which schematically shows a phase-changeable memory cell. Referring to FIG. 2, the typical phase-changeable memory device includes a lower conductive pattern 10, a phase-changeable material pattern 16 and an upper conductive pattern 18. The phase-changeable material pattern 16 is electrically connected to the lower conductive pattern 10 through a contact plug 14 formed in an insulating layer 12. The insulating layer 12 is disposed on the lower conductive pattern 10. The upper conductive pattern 18 is formed on the phase-changeable material pattern 16. In the typical phase-changeable memory device, if currents flow between the lower conductive pattern 10 and the upper conductive pattern 18, the crystallization state of the phase-changeable material varies in accordance with a pulse (i.e., heat) of the currents flowing through an area (hereinafter referred to as “active contact area”) 20 where the contact plug 14 is in contact with the phase-changeable material pattern 16. The heat (i.e., energy) required to change the state of the phase-changeable material is directly affected by the active contact area 20 where the phase-changeable material pattern 16 is in contact with the contact plug 14. Preferably, the active contact area 20 should be made as small as possible.
However, because the lower conductive pattern 10 is connected to the phase-changeable material pattern 16 through the contact plug 14, a size of the active contact area 20 may be limited by a photolithography resolution for the contact hole, i.e., the size of the active contact area 20 generally cannot be reduced beyond the photolithography resolution. Furthermore, it may be difficult to form such contact holes uniformly in the memory device, which can result in variance in current flow for changing the state of the phase-changeable material for each contact area. Thus, mis-operation in read mode can easily occur. Also, because only one active contact area 20 is formed at the area that is in contact with the contact plug 14, a resistance variation resulting from the variation of the crystallization state is small.